CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

5.2 External Signal Functions

Function

Data bus

Address bus

Memory

Interface

Signal

Name

Signal

Description

D[0-31]

I/O 32-bit system data bus for memory, DRAM, and I/O interface

A[0-14]

O 15 bits of system byte address during memory and expansion cycles

A[13-27]

DRA[0-14]

DRA[0-14] is multiplexed with A[13-27], offering additional power sav-

ings since the lightest loading is expected on the high order ROM

address lines.

Whenever the CS89712 is in the Standby State, the external address

and data buses are driven low. The RUN signal is used internally to

force these buses to be driven low. This is done to prevent peripher-

als that are powered-down from draining current. Also, the internal

peripheral’s signals get set to their Reset State.

BA[0-1]/A[13/14]

I/O SDRAM bank select pins.

SDCS[0-1] A2, E3 O SDRAM chip selects.

SDCLK

E2

O SDRAM clock.

SDCKE

D2

O SDRAM clock enable.

SDQM[2-3] C2, B2

SDRAM byte masks. SDQM0-1 are muxed with Port D data pins.

nMOE/nSDCAS D16

O Memory output enable/SDRAM CAS control signal

nMWE/nSDWE E10

O Memory write enable/SDRAM write enable control signal

nCS[0-1, 3] A1, B1, O Chip select; active low, SRAM-like chip selects for expansion

C1

Ethernet Enable G12,

/ nCS2

H13

O Chip select; active low, indicates either Ethernet port or CS2 expan-

sion range activity. Pins G12 and H13 must be tied together.

nCS[4-5] D1, F2 O Chip select; active low, CS for expansion or for CL-PS6700 select

EXPRDY

G3

I Expansion port ready; external expansion devices drive this low to

extend the bus cycle. This is used to insert wait states for an external

bus cycle.

WRITE

G1

O Write strobe, low during reads, high during writes from the CS89712

WORD/

F1

HALFWORD T15

O To do write accesses of different sizes Word and Half-Word must be

externally decoded. The encoding of these signals is as follows:

Access Size

Word

Half-Word

Byte

Word

1

*

0

Half-Word

0

1

0

Interrupts

EXPCLK

nMEDCHG/

nBROM

nEXTFIQ

nEINT[1:2]

E1

I/O Expansion clock rate is the same as the CPU clock for 18 MHz. It

runs at 36.864 MHz for 36,49 and 74 MHz modes.

J12

I Media changed input; active low, deglitched. Used as a general pur-

pose FIQ interrupt during normal operation. It is also used on power

up to configure the processor to either boot from the internal Boot

ROM, or from external memory. When low, the chip will boot from the

internal Boot ROM.

N4

I External active low fast interrupt request input

N2, P1 I Two general purpose, active low interrupt inputs

Table 90. External Signal Functions

DS502PP2

141

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