CS4630
12.1 PCI Interface
AD[31:0] - Address / Data Bus, I/O
These pins form the multiplexed address/data bus for the PCI interface.
C/BE[3:0]# - Command Type / Byte Enables, I/O
These four pins are the multiplexed command/byte enables for the PCI interface. During the
address phase of a transaction, these pins indicate cycle type. During the data phases of a
transaction, active low byte enable information for the current data phase is indicated. These
pins are inputs during slave operation and they are outputs during bus mastering operation.
PAR - Parity, I/O, Active High
The Parity pin indicates even parity across AD[31:0] and C_BE[3:0] for both address and data
phases. The signal is delayed one PCI clock from either the address or data phase for which
parity is generated.
FRAME# - Cycle Frame, I/O, Active Low
FRAME# is driven by the current PCI bus master to indicate the beginning and duration of a
transaction.
IRDY# - Initiator Ready, I/O, Active Low
IRDY# is driven by the current PCI bus master to indicate that as the initiator it is ready to
transmit or receive data (complete the current data phase).
TRDY# - Target Ready, I/O, Active Low
TRDY# is driven by the current PCI bus target to indicate that as the target device it is ready to
transmit or receive data (complete the current data phase).
STOP# - Transition Stop, I/O, Active Low
STOP# is driven active by the current PCI bus target to indicate a request to the master to stop
the current transaction.
IDSEL - Initialize Device Select, Input, Active High
IDSEL is used as a chip select during PCI configuration read and write cycles.
DEVSEL# - Device Select, I/O, Active Low
DEVSEL# is driven by the PCI bus target device to indicate that it has decoded the address of
the current transaction as its own chip select range.
REQ# - Master Request, Three-State Output, Active Low
REQ# indicates to the system arbiter that this device is requesting access to the PCI bus. This
pin is high-impedance when RST# is active.
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DS445PP1