CS4630-CM View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4630-CM Datasheet PDF : 38 Pages
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CS4630
11. PCI POWER MANAGEMENT
The CS4630 supports the PCI Bus Power Manage-
ment Interface Specification (version 1.1). The
CS4630 supports all power states and is capable of
PME# generation from D0 - D3hot, and D3cold pro-
vided auxillary 3.3V power is available
The PCI power management specification defines
four major power states: D0 (fully on), D1, D2, and
D3 (fully off). The D3 state is divided into two sub-
states, D3hot and D3cold. D3cold differs from
D3hot in that the normal PCI bus Vcc power sourc-
es are turned off.
11.1 D0 State
The D0 state is divided into two substates,
D0active and D0uninitialized. The D0unitialized
state describes a device that has just received a PCI
RST# signal and has not yet been programmed;
therefore, it is not consuming full power. The
D0active state describes a device that has been pro-
grammed and is fully operational.
The CS4630 must initially be put into D0 before
being used. Upon entering D0 from power on reset,
or transition from D3cold, the CS4630 will be in an
uninitialized state. Once initialized by the system
software, it will transition to the D0active state.
CS4630 Operation during D0 state:
• Phase Lock Loop - Running
• SP Clock
- Running
• SP RAM Clock - Running
• AC Link
- Running
11.2 Dl State
Dl is used as a light sleep state. All necessary inter-
nal state information and data samples are pre-
served while in D1. The transition back to D0 state
will occur within 100ms.
CS4630 Operation during D1 state:
• Phase Lock Loop - Running
• SP Clock
- Stopped
• SP RAM Clock - Running
• AC Link
- Running
11.3 D2 State
This state requires significant power savings while
still retaining the abi1ity to recover to a previous
condition. The transition back to D0 state will oc-
cur within 100ms.
CS4630 Operation during D2 state:
• Phase Lock Loop - Running
• SP Clock
- Stopped
• SP RAM Clock - Stopped
• AC Link
- Running
11.4 D3hot State
In this state, function context need not be main-
tained. When the CS4630 is brought back to D0
(the only legal state transition from D3), software
will perform a full reinitialization of the CS4630
including its PCI Configuration Space.When pro-
grammed to D0 from D3, the CS4630 performs the
equivalent of a warm reset and returns to the
D0uninitialized state without PCI RST# being as-
serted.
CS4630 Operation during D3hot state:
• Phase Lock Loop - Stopped
• SP Clock
- Stopped
• SP RAM Clock - Stopped
• AC Link
- Stopped
11.5 D3cold State
When Vcc is removed from the PCI Bus and PCI
RST# is asserted, the CS4630 will transition imme-
diately to D3cold. When power is restored, PCI
RST# will be de-asserted and the CS4630 will re-
turn to D0uninitialized state with a full PCI 2.1
compliant power on reset sequence whenever
PME# has not been enabled.
If the CS4630 is enabled to generate a PME# event
from the D3 power state, and an auxillary 3.3 V
power source is available, no logic within the chip
will be reset during the assertion of PCI RST#
while the main system 3.3 V is removed.
CS4630 Operation during D3cold state:
• Phase Lock Loop - Stopped
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