CS4630-CM View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4630-CM Datasheet PDF : 38 Pages
| |||
CS4630
• SP Clock
- Stopped
• SP RAM Clock - Stopped
• AC Link
- Stopped
11.6 CS4630 PME# Assertion
Two methods are supported by the CS4630 in gen-
erating a PME# event to the PCI Bus. Method one,
with ABITCLK running, is primarily used when
the SP is required to perform a processing task such
as discriminating a valid Ring condition from the
DAA or decode incoming Caller-ID information.
The other method is used when maximum power
savings is required (both ABITCLK and PCI CLK
are off) and the SP is not needed for signal process-
ing.
11.6.1 ABITCLK ON
The CS4630, with ABITCLK running, can assert
PME# from the D0, D1, D2, D3hot and D3cold
power management device states in response to
software executing on the SP.
The CS4630 SP and logic that generates this inter-
nal event and asserts PME# is clocked from the AC
‘97 ABITCLK signal when connected to an AC ‘97
Codec. While in this mode, the AC Link is not al-
lowed to be powered down by setting the PR4 bit
the AC ‘97 codec. ABITCLK must be allowed to
run.
CS4630 Operation with PME# generation enabled
and ABITCLK running:
• Phase Lock Loop - Running at reduced rate
• SP Clock
- Running at reduced rate
• SP RAM Clock - Running at reduced rate
• AC Link
- Running
11.6.2 ABITCLK OFF
Due to the short recovery times from D1 and D2
power states, the CS4630 will only support asser-
tion of PME# from the D3hot and D3cold power
management device states while the codec is in
PR4 power state with ABITCLK off. With ABIT-
CLK off, the CS4630 will generate a PME# event
in response to a low-to-high transition on the AS-
DIN or ASDIN2 pin when the CS4630 is config-
ured for AC ‘97 operation and the AC link is down
(codec in PR4). Codecs compliant with the AC ‘97
2.0 specification use this mechanism to signal a
wake-up event to the AC ‘97 controller.
CS4630 Operation with PME# generation enabled
and ABITCLK stopped
• Phase Lock Loop - Stopped
• SP Clock
- Stopped
• SP RAM Clock - Stopped
• AC Link
- Stopped
11.7 On Card Vaux Switching Logic
Three new signal I/O are required for support of
PME generation from D3cold on the CS4630 de-
vice. Vaux_Sense is an input pin used by the PCI
Configuration Registers to determine if 3.3 Vaux is
present on the PCI Bus. The signal level on this pin
determines the value presented in the Power Man-
agement Capabilities register at offset 0x42.
Vaux_Sense will contain an internal pull-down re-
sistor to maintain backwards compatibility.
PCIVdd_Sense is an input pin used to sense the
main system 3.3 V to determine when D3cold pow-
er state has begun and to block the PCI RST# signal
from causing a reset condition to critical logic.
PCIVdd_Sense will contain an internal pull-down
resistor to maintain backwards compatibility. An
output pin, Vaux_Sel, is used to control external
power MOSFET transistors which switch the
CS4630’s voltage supply from Main 3.3 Vcc to 3.3
Vaux. If 3.3 Vaux is used to supply power during
D3cold and VDD5REF is tied to +5 V, then a low
Vf Schottky diode, similar to a standard BAT54 de-
vice, is required to be placed in series with the
VDD5REF signal. No diode is require if
VDD5REF is tied to 3.3 Vaux.
DS445PP1
27
Share Link: 