CS4630-CM View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4630-CM Datasheet PDF : 38 Pages
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CS4630
7. EEPROM INTERFACE
The EEPROM configuration interface allows the
connection of an optional external EEPROM de-
vice to provide power-up configuration informa-
tion. The external EEPROM is not required for
proper operation; however, in some applications
power-up configuration settings other than the de-
fault values may be required to support specific op-
erating system compatibility requirements.
After a hardware reset, an internal state machine in
the CS4630 will automatically detect the presence
of an external EEPROM device (assuming EEPDIS
is low) and load the Subsystem ID and Subsystem
Vendor ID fields, along with two bytes of general
configuration information, into internal registers.
At power-up, the CS4630 will attempt to read from
the external device, and will check the data re-
ceived from the device for a valid signature header.
If the header data is invalid, the data transfer is
aborted. After power-up, the host can read or write
from/to the EEPROM device by accessing specific
registers in the CS4630. Cirrus Logic provides soft-
ware to read and write the EEPROM.
The two-wire interface for the optional external
EEPROM device is depicted in Figure 14. During
data transfers, the data line (EEDAT) can change
state only while the clock signal (EECLK) is low.
A state change of the data line while the clock sig-
nal is high indicates a start or stop condition to the
EEPROM device.
The EEPROM device read access sequence is
shown in the Figure 15. The timing follows that of
a random read sequence. The CS4630 first per-
forms a “dummy” write operation, then generates a
start condition followed by the slave device address
and the byte address of zero. The CS4630 always
begins access at byte address zero and continues
access a byte at a time, using a sequential read, until
all needed bytes in the EEPROM are read. Since
only a maximum of 12 bytes are needed, the small-
est EEPROM available will suffice.
SLIMD SP
Core
EEDAT
EECLK
4.7 kΩ
2-wire
Serial
EEPROM
Figure 14. External EEPROM Connection
CS46XX
Part
Bank
Start Address Write Address
Start
Part Read
Address
S1 0 1 0 0 0 0 0A0 0 0 0 0 0 0 0AS1 0 1 0 0 0 0 1A
EEPROM
Acknowledge
No
Acknowledge Acknowledge
Stop
Data
A
Data 1 P
Data
Figure 15. EEPROM Read Sequence
DS445PP1
23
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