MT90823
Data Sheet
ST-BUS Frame
CLK
Offset Value
FE Input
GCI Frame
CLK
Offset Value
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK low phase)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FE Input
(FD[10:0] = 09H)
(FD11 = 1, sample at CLK high phase)
Figure 4 - Example for Frame Alignment Measurement
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Zarlink Semiconductor Inc.