MT90823AL1 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

MFG CO.

MT90823AL1

3 V Large Digital Switch

Zarlink Semiconductor Inc 

MT90823

Data Sheet

Read Address:

Reset Value:

02H,

0000H.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0

0

0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0

Bit

15 - 13

12

11

10 - 0

Name

Unused

CFE

FD11

FD10-0

Description

Must be zero for normal operation.

Complete Frame Evaluation. When CFE = 1, the frame evaluation is

completed and bits FD10 to FD0 bits contains a valid frame alignment offset.

This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to

0.

Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is

sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase

(FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle.

Frame Delay Bits. The binary value expressed in these bits refers to the

measured input offset value. These bits are reset to zero when the SFE bit of

the IMS register changes from 1 to 0. (FD10 = MSB, FD0 = LSB)

Table 10 - Frame Alignment (FAR) Register Bits

18

Zarlink Semiconductor Inc.

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