MT90823AL1 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
MT90823AL1 Datasheet PDF : 46 Pages
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MT90823
Data Sheet
A7
(Note 1)
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0 Control Register, CR
0
0
0
0
0
0
0
1 Interface Mode Selection Register, IMS
0
0
0
0
0
0
1
0 Frame Alignment Register, FAR
0
0
0
0
0
0
1
1 Frame Input Offset Register 0, FOR0
0
0
0
0
0
1
0
0 Frame Input Offset Register 1, FOR1
0
0
0
0
0
1
0
1 Frame Input Offset Register 2, FOR2
0
0
0
0
0
1
1
0 Frame Input Offset Register 3, FOR3
1
0
0
0
0
0
0
0 Ch 0
1
0
0
0
0
0
0
1 Ch 1
1
0
0
.
.
.
.
..
1
0
0
1
1
1
1
0 Ch 30
1
0
0
1
1
1
1
1 Ch 31
(Note 2)
1
0
1
0
0
0
0
0 Ch 32
1
0
1
0
0
0
0
1 Ch 33
1
0
1
.
.
.
.
..
1
0
1
1
1
1
1
0 Ch 62
1
0
1
1
1
1
1
1 Ch 63
(Note 3)
1
1
0
0
0
0
0
0 Ch 64
1
1
0
0
0
0
0
1 Ch 65
1
1
.
.
.
.
.
..
1
1
1
1
1
1
1
0 Ch 126
1
1
1
1
1
1
1
1 Ch 127
(Note 4)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2Mb/s mode.
3. Channels 0 to 63 are used when serial interface is at 4Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8Mb/s mode.
Table 4 - Internal Register and Address Memory Mapping
OE bit in Connection
Memory
ODE pin
OSB bit in IMS register ST-BUS Output Driver Status
0
Don’t Care
Don’t Care
Per Channel
High Impedance
1
0
0
High Impedance
1
0
1
Enable
1
1
Don’t care
Enable
Table 5 - Output High Impedance Control
If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of
the frame delay offset registers must be set to zero.
15
Zarlink Semiconductor Inc.
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