MT90823AL1 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
MT90823AL1 Datasheet PDF : 46 Pages
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MT90823
Data Sheet
Initialization of the MT90823
During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the
normal functional mode. A 5K pull-down resistor can be connected to this pin so that the device will not enter the
JTAG test mode during power up.
Upon power up, the contents of the connection memory can be in any state and the ODE pin should be held low to
keep all ST-BUS outputs in a high impedance state until the microprocessor has initialized the switching matrix.
To prevent two ST-BUS outputs from driving the same stream simultaneously, the microprocessor should program
the desired active paths through the switch and put all other channels into a high impedance state during the
initialization routine by using the block programming mode. In addition, the loopback bits in the connection memory
should be cleared for normal operation.
When this process is complete, the microprocessor controlling the matrices can bring the ODE pin or OSB bit high
to relinquish the high impedance state control to the OE bit in the connection memory.
Read/Write Address:
Reset Value:
00H,
0000H.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
0
0 MBP MS STA3 STA2 STA1 STA0
Bit
15 - 6
5
4
3-0
Name
Unused
MBP
MS
STA3-0
Description
Must be zero for normal operation.
Memory Block Program. When 1, the connection memory block programming
feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15.
When 0, this feature is disabled.
Memory Select. When 0, connection memory is selected for read or write operations.
When 1, the data memory is selected for read operations and connection memory is
selected for write operations. (No microprocessor write operation is allowed for the
data memory.)
Stream Address Bits. The binary value expressed by these bits refers to the input or
output data stream, which corresponds to the subsection of memory made accessible
for subsequent operations. (STA3 = MSB, STA0 = LSB)
Table 6 - Control (CR) Register Bits
Input/Output
Data Rate
Valid Address Lines
2.048 Mb/s
A4, A3, A2, A1, A0
4.096 Mb/s
A5, A4, A3, A2, A1, A0
8.192 Mb/s
A6, A5, A4 A3, A2, A1, A0
Table 7 - Valid Address lines for Different Bit Rates
16
Zarlink Semiconductor Inc.
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