CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

MCLK

DRA[12:0]

RAS[1:0]

CAS[3:0]

D[31:0]

DRAM CAS before RAS refresh cycle (MCLK shown for reference only)

HELD

tCSA

tRC

tRAS

ROW

COL

HELD

NMOE

NMWE

Figure 6-7. DRAM CAS-Before-RAS Refresh Cycle

NOTES:

1) tCSA (CAS set-up time) = 15 ns minimum at MCLK = 18.432 MHz, and 20 ns at 13.0 MHz

2) tRAS (RAS pulse width) = 80 ns minimum at MCLK = 18.432 MHz, and 110 ns at 13.0 MHz

3) tRC (cycle time) = 160 ns minimum at MCLK = 18.432 MHz, and 230 ns at 13.0 MHz

4) When DRAMs are placed in self-refresh (entering standby) the same timings apply, but tRAS is extended

indefinitely.

September 1997

PRELIMINARY DATA BOOK v2.0

85

ELECTRICAL SPECIFICATIONS

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