MCLK
DRA[12:0]
RAS0
CAS[3:0]
D[31:0]
NMOE
NMWE
CL-PS7111
Low-Power System-on-a-Chip
Video quad word read (MCLK shown for reference only)
tVACC
ROW
tRP
COL 0 COL 1 COL 2 COL 3
tCAS
tCP
tPC
0
1
2
3
Figure 6-6. Video Quad Word Read from DRAM
NOTES:
1) Timings are the same as Page mode word reads.
2) tVACC (video access cycle time) = 326 ns at MCLK = 18.432 MHz, and 462 ns at 13.0 MHz
84
ELECTRICAL SPECIFICATIONS
September 1997
PRELIMINARY DATA BOOK v2.0