CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4

GRAYSCALE

GRAYSCALE

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

4-BITS-PER-PIXEL

PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4

GRAYSCALE GRAYSCALE GRAYSCALE GRAYSCALE

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

2-BITS-PER-PIXEL

PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

1-BIT-PER-PIXEL

Figure 3-6. Video Buffer Mapping

The refresh rate is not affected by the number of bits per pixel. However, the LCD controller fetches twice

the data per refresh for 4-bits-per-pixel compared to 2-bits-per-pixel. The main reason for reducing the

number of bits per pixel is to reduce the power consumption of the memory where the video buffer is

mapped.

3.11 Two Internal UARTs and SIR Encoder

The CL-PS7111 contains two built-in UART, UART1 and UART2. Both UARTs support bit rates of up to

115.2 kbps and contain two 16-byte FIFOs for receive and transmit.

UART1 supports the three modem-control input signals: CTS, DSR, and DCD. The additional RI input

modem control line is not supported. Output modem control lines (such as RTS and DTR) are not explic-

itly supported, but can be implemented using bits from the GPIO ports in the CL-PS7111. UART2 has

only receive and transmit pins.

34

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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