CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

An example of the DRAM connections for a typical system can be found in Figure 3-3 on page 20.

Table 3-10 and Table 3-11 show the address mapping for various DRAMs with square and non-square

row and address inputs, assuming two ×16 devices are connected to each RAS line, with 32-bit-wide

DRAM operation selected. This mapping is then repeated every 256 Mbytes for each DRAM bank. n is

derived as shown in Equation 3-1.

n = 0 × C + bank number

Equation 3-1

where,

0 × C for bank 0

0 × D for bank 1)

Table 3-10. DRAM Address Mapping for an External 32-Bit-Wide DRAM Memory System

Device Size

Address

Configuration

Total Size of Bank

Address Range of

Segment(s)

Size of Segment(s)

4 Mbits

16 Mbits

9 Row × 9 Column

10 Row × 10 Column

16 Mbits

12 Row × 8 Column

64 Mbits 11 Row × 11 Column

64 Mbits

13 Row × 9 Column

256 Mbits

1 Gbit

12 Row × 12 Column

13 Row × 13 Column

1 Mbyte

4 Mbytes

4 Mbytes

16 Mbytes

16 Mbytes

64 Mbytes

256 Mbytes

n000.0000–n00F.FFFF

n000.0000–n03F.FFFF

n000.0000– n007.FFFF

n010.0000–n017.FFFF

n040.0000–n047.FFFF

n050.0000–n057.FFFF

n100.0000–n107.FFFF

n110.0000–n117.FFFF

n140.0000–n147.FFFF

n150.0000–n157.FFFF

n000.0000–n0FF.FFFF

n000.0000–n01F.FFFF

n040.0000–n05F.FFFF

n100.0000–n11F.FFFF

n140.0000–n15F.FFFF

n400.0000–n41F.FFFF

n440.0000–n45F.FFFF

n500.0000–n51F.FFFF

n540.0000–n55F.FFFF

n000.0000–n3FF.FFFF

n000.0000–nFFF.FFFF

1 Mbyte

4 Mbytes

512 Kbytes

16 Mbytes

2 Mbytes

64 Mbytes

256 Mbytes

September 1997

PRELIMINARY DATA BOOK v2.0

31

FUNCTIONAL DESCRIPTION

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