CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

3.10 LCD Controller

The LCD controller provides all the necessary control signals to interface directly to a single-scan panel

multiplexed LCD. The panel size is programmable and can be any width (line length) from 16 to 1024 pix-

els in 16-pixel increments. The total video frame size is programmable up to 128 Kbytes. This equates to

a theoretical maximum panel size of 1024 × 256 pixels in 4-bits-per-pixel mode. The video frame buffer

can be located in any portion of memory controlled by the chip select or system DRAM. Its start address

will be fixed at address 0xC000.0000 within each chip select or DRAM bank. The start address of the LCD

frame buffer is defined in FBADDR register [3:0]. The default start address is 0xC000 0000 (FBADRR

=0x0C). A system can be built using no DRAM. One option is to use the on-chip 2-Kbyte SRAM as the

LCD buffer for small panels. In this option, the LCD frame buffer start address must be set to 0x6. Pro-

gramming of FBADDR is permitted only when the LCD is disabled. (This is to avoid possible cycle cor-

ruption when changing the register contents while a LCD DMA cycle is in progress.) There is no hardware

protection to prevent this, so it is necessary for the software to disable the LCD controller before repro-

gramming FBADDR. The frame buffer start address must not be programmed to 0x4 or 0x5 if either

CL-PS6700 interface is in use (PCMEN1 or 2 bits in the SYSCON2 register enabled).

NOTE: Never program FBADDR to 0x7 or 0x8 as these are the locations for the on-chip Boot ROM and internal

registers.

The screen is mapped to the frame buffer as one contiguous block where each horizontal line of pixels is

mapped to a set of consecutive bytes or words in the frame buffer. The frame buffer can be accessed

word-wide as pixel 0 is mapped to the LSB in the buffer, the pixels arranged in a little-endian scheme.

The pixel bit rate and the LCD refresh rate can be programmed from 18432 – 576 kHz when operating in

the 18.432-MHz mode, or 1300 – 203 kHz when operating from a 13-MHz clock. The LCD controller is

programmed by writing to LCDCON. Programming LCDCON while the LCD controller is enabled causes

the DMA address generator to be reset and a new frame to be started immediately.

The LCD controller also contains two 32-bit palette registers, allowing any 4-, 2-, or 1-bit pixel value to be

mapped to any one of the available 16 grayscale values.

The required DMA bandwidth to support a half-VGA panel (640 × 240) displaying 4-bits per pixel data at

an 80-Hz refresh rate is approximately 6.2 Mbytes/sec. Assuming the frame buffer is stored in DRAM, the

maximum theoretical bandwidth available is 43 Mbytes/sec. at 18.432 MHz, or 29.7 Mbytes/sec. at 13

MHz. If 16-bit DRAM is used, this drops to 15 Mbytes/sec., still leaving sufficient bandwidth for other mem-

ory activity.

The LCD controller uses a 9-stage 32-bit-wide FIFO to buffer display data, which is replenished by hard-

ware DMA under the control of the CL-PS7111 DMA controller. The LCD controller module requests new

data when there are five words remaining in the FIFO, meaning for a half-VGA panel displaying 4-bitsper-

pixel data at an 80-Hz refresh rate, the maximum allowable DMA latency is approximately 3.2 µs. Assum-

ing the frame buffer is located in DRAM memory, the worst case latency is almost exactly 3.2 µs, with

13-MHz page mode cycles. If 16-bit-wide DRAM is being used, the worst case latency will double. In this

case, the maximum permissible display size is halved to approximately 320 × 240 pixels, assuming the

same refresh rate must be maintained.

Figure 3-6 shows the organization of the video map for all combinations of bits per pixel.

September 1997

PRELIMINARY DATA BOOK v2.0

33

FUNCTIONAL DESCRIPTION

Share Link: