CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CL-PS7111-VC-A Datasheet PDF : 105 Pages
| |||
CL-PS7111
Low-Power System-on-a-Chip
Table 3-11. DRAM Address Mapping for a 16-bit DRAM Memory System
Device Size
Address
Configuration
Total Size of Bank
Address Range of
Segment(s)
Size of Segment(s)
4 Mbits
16 Mbits
9 Row × 9 Column
10 Row × 10 Column
16 Mbits
12 Row × 8 Column
64 Mbits 11 Row × 11 Column
64 Mbits
13 Row × 9 Column
256 Mbits
1 Gbit
12 Row × 12 Column
13 Row × 13 Column
0.5 Mbyte
2 Mbytes
2 Mbytes
8 Mbytes
8 Mbytes
32 Mbytes
128 Mbytes
n000.0000– n007.FFFF
n000.0000–n01F.FFFF
n000.0000–n003.FFFF
n008.0000–n00B.FFFF
n020.0000–n023.FFFF
n028.0000–n02B.FFFF
n080.0000–n083.FFFF
n088.0000–n08B.FFFF
n0A0.0000–n0A3.FFFF
n0A8.0000–n0AB.FFFF
n000.0000–n07F.FFFF
n000.0000–n00F.FFFF
n020.0000–n02F.FFFF
n080.0000–n08F.FFFF
n0A0.0000–n0AF.FFFF
n200.0000–n20F.FFFF
n220.0000–n22F.FFFF
n280.0000–n28F.FFFF
n2A0.0000–n2AF.FFFF
n000.0000–n1FF.FFFF
n000.0000–n7FF.FFFF
0.5 Mbyte
2 Mbytes
256 Kbytes
8 Mbytes
1 Mbyte
32 Mbytes
128 Mbytes
The DRAM controller contains a programmable refresh counter. The refresh rate is controlled using
DRFPR (DRAM Refresh Period register ).
Sixteen- or 32-bit DRAM selection is made based on the value of SYSCON2[2]. Both banks must have
the same width.
SYSCON2
0 × 8000 1100
Bit 2 (DRAMSZ) 0 = 32-bit DRAM
1 = 16-bit DRAM
The default DRAM width is 32 bits, because SYSCON2 is reset to all zeroes at power up.
32
FUNCTIONAL DESCRIPTION
September 1997
PRELIMINARY DATA BOOK v2.0
Share Link: 