CL-PS7111
Low-Power System-on-a-Chip
Port B Data Direction 47
Port D Data 47
Port D Data Direction 47
Port E Data 47
Port E Data Direction 47
programming interface 69
Pump Control 45, 63
Realtime Clock Data 39, 45
Realtime Clock Match 62
SYSCON1 41
SYSCON2 25, 39
System Control 22, 45, 48
system control 70
System Status Flags 45, 50, 71
UART Bit Rate and Line Control 35, 45, 51, 58, 65
UART Data 64
UART Rx 37
resets, asynchronous 39–40
S
software-selectable test functionality 90
SPI 2, 18, 41, 48
states
idle 24, 38
operating 24, 38
standby 24, 38
system configuration, maximum 20
T
timer counters 22
timing
DRAM CAS-Before-RAS Refresh Cycle 85
DRAM Read Cycles 80
DRAM Write Cycles 82
Expansion and ROM Read 77
Expansion and ROM Write 78–79
LCD Controller 86
Video Quad Word Read 84
U
UART 1–2, 19, 34
V
video buffer mapping 34
September 1997
PRELIMINARY DATA BOOK v2.0
103
OVERVIEW