CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

Functional (EPB) Test 88

High-Z (System) Test 89

Oscillator and PLL Bypass 88

Oscillator and PLL Test 88

Pin Test 89

Page 25, 54

timing 76–80

Prescale 23, 49

Self-refresh 57

Standby 69

System Test (High-Z) 87

N

NPOR. See resets, asynchronous

NPWRFL. See resets, asynchronous

NSYSRES. See resets, asynchronous

NURESET. See resets, asynchronous

O

operating conditions, recommended 73

ordering information 92

P

PCMCIA

reads 29

writes 28

pin diagram 8

pin information

A[0–27] 9

ADCCLK 10

ADCIN 10

ADCOUT 10

BATOK 9

BUZ 11

CL[1–2] 10

COL[0–7] 11

conventions 7

CTS 10

D[0–31] 9

DCD 10

DD[0–3] 10

DRA[12–0] 9

DRIVE[0–1] 11

DSR 10

EINT[3] 9

EXPCLK 9

EXPRDY 9

FB[0–1] 11

FRM 10

LEDDRV 10

M 10

MEDCHG 9

102

OVERVIEW

CL-PS7111

Low-Power System-on-a-Chip

MOSCIN/ MOSOUT 11

NADCCS 10

NBATCHG 9

NCAS[0–3] 9

NCS[0–3] 9

NCS[4–5] 9

NEINT[1–2] 9

NEXTFIQ 9

NEXTPWR 9

NMOE 9

NMWE 9

NPOR 10

NPWRFL 9

NRAS[0–3] 9

NTEST[0–1] 11

numeric pin listing 12

NURESET 10

PA[0–7] 11

PB[0–7] 11

PCMCK 10

PCMIN 10

PCMOUT 10

PCMSYNC 10

PD[0–7] 11

PE[0–3] 11

PHDIN 10

RTCIN/ RTCOUT 11

RUN 10

RxD 10

SMPLCK 10

TxD 10

WAKEUP 10

WORD 9

WRITE 9

R

realtime clock 23

registers

Codec Interface Data 64

DRAM Refresh Period 32, 39–40, 57

internal I/O memory locations table 44

Interrupt Mask 37, 45, 60, 72

Interrupt Status 37, 58, 72

See also ARM710A Data Sheet

LCD Control 45, 60

Least-Significant Word-LCD Palette(PALLSW) 68

Memory Configuration Register 1 45, 53

Memory Configuration Register 2 54

Most-Significant Word-LCD Palette(PALMSW) 68

Output Shift 42

Port A Data 47

Port A Data Direction 47

September 1997

PRELIMINARY DATA BOOK v2.0

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