C8051T603-GS(2007) View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051T603-GS Datasheet PDF : 168 Pages
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C8051T600/1/2/3/4/5
SFR Definition 5.4. ADC0CF: ADC0 Configuration
R/W
AD0SC4
Bit7
R/W
AD0SC3
Bit6
R/W
AD0SC2
Bit5
R/W
AD0SC1
Bit4
R/W
AD0SC0
Bit3
R/W
R/W
R/W
Reset Value
AD08BE AMP0GN1 AMP0GN0 11111000
Bit2
Bit1
Bit0 SFR Address:
0xBC
Bits7–3:
Bit2:
Bits1–0:
AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock require-
ments are given in Table 5.1.
Note: if the OTP Power Controller is enabled (OTPPCE = '1'), AD0SC must be set to at
least "00001" for proper ADC operation.
AD0SC = S----Y----S---C----L----K-- – 1
CLKSAR
AD08BE: 8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
AMP0GN1–0: ADC Gain Control Bits.
00: Gain = 0.5
01: Gain = 1
SFR Definition 5.5. ADC0H: ADC0 Data Word High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
D9
D8
D7
D6
D5
D4
D3
D2 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xBE
Bits7–0:
ADC0 Data Word bits 9–2.
ADC0H holds the upper 8 bits of output data from the most recently completed ADC0 con-
version. In 8-bit compatibility mode, the ADC0H register holds all 8 bits of the conversion
data word.
SFR Definition 5.6. ADC0L: ADC0 Data Word Low Byte
R/W
R/W
R
R
R
R
R
R
Reset Value
D1
D0
-
-
-
-
-
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xBD
Bits7–6:
Bits5–0:
ADC0 Data Word bits 1–0.
Read: 000000b, Write = Don’t Care
ADC0L holds the lowest 2 bits of output data from the most recently completed ADC0 con-
version. In 8-bit compatibility mode, the ADC0L register always returns 0x00.
40
Rev. 0.5
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