C8051T603-GS(2007) View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051T603-GS
(Rev.:2007)

Mixed Signal OTP EPROM MCU Family

Silicon Laboratories 

C8051T600/1/2/3/4/5

5.6.2. Tracking Modes

The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion

start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left

at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conver-

sion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is

used to initiate conversions, ADC0 will track either when AD0TM is logic 1, or when AD0TM is logic 0 and

CNVSTR is held low. See Figure 5.4 for track and convert timing details. Delayed conversion mode is use-

ful when AMUX settings are frequently changed, due to the settling time requirements described in Sec-

tion “5.6.3. Settling Time Requirements” on page 38.

CNVSTR

(AD0CM[2:0] = 1xx)

SAR

Clocks

A. ADC Timing for External Trigger Source

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17

AD0TM = 1

SAR Clocks

Track

Convert

Track

*Conversion Ends at rising edge of 15th clock in 8-bit Compatibility Mode

1 2 3 4 5 6 7 8 9 10 11 12* 13 14

AD0TM = 0 N/C Track

Convert

N/C

Write '1' to AD0BUSY,

Timer 0, Timer 2, Timer 1 Overflow

(AD0CM[2:0] = 000, 001, 010, 011)

*Conversion Ends at rising edge of 12th clock in 8-bit Compatibility Mode

B. ADC Timing for Internal Trigger Source

SAR

Clocks

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17

AD0TM = 1

Track

Convert

Track

*Conversion Ends at rising edge of 15th clock in 8-bit Compatibility Mode

SAR

Clocks

AD0TM = 0

1 2 3 4 5 6 7 8 9 10 11 12* 13 14

Track or

Convert

Convert

Track

*Conversion Ends at rising edge of 12th clock in 8-bit Compatibility Mode

Figure 5.4. ADC Tracking and Conversion Timing

Rev. 0.5

37

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