C8051T603-GS(2007) View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051T603-GS
(Rev.:2007)

Mixed Signal OTP EPROM MCU Family

Silicon Laboratories 

C8051T600/1/2/3/4/5

5.1. Analog Multiplexer

The analog multiplexer (AMUX0) selects the positive input to the ADC, allowing any Port pin to be mea-

sured relative to GND. Additionally, the on-chip temperature sensor or the positive power supply (VDD)

may be selected as the positive ADC input. The ADC0 input channel is selected in the AMX0SL register as

described in Figure 5.3. When an external Voltage Reference is supplied to P0.0 or the internal regulator is

used as VREF, the VDD Voltage supply can be determined by taking a measurement of VDD with the gain

setting at 0.5x.

Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-

ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog

input, clear the corresponding bit in register P0MDIN to ‘0’. To force the Crossbar to skip a Port pin, set the

corresponding bit in register XBR0 to ‘1’. See Section “13. Port Input/Output” on page 97 for more Port

I/O configuration details.

5.2. Gain Setting

The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined

directly by VREF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is VREF x 2.

The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small VREF volt-

age, or to measure input voltages that are between VREF and VDD. Gain settings for the ADC are con-

trolled by the AMP0GN1–0 bits in register ADC0CF.

5.3. Output Coding

The conversion code format for the ADC is shown below. Conversion codes are represented as 10-bit

unsigned integers. Inputs are measured from ‘0’ to VREF x 1023/1024. All conversions are left-justified in

the ADC0H and ADC0L registers (ADC0H holds the 8 most significant bits, and the two least significant

bits are stored in ADC0L). Example codes are shown below.

Input Voltage

(AIN – GND),

Gain = 1

VREF x 1023/1024

VREF/2

VREF/4

0

10-bit Output (Conversion Code)

0x3FF

0x200

0x100

0x00

ADC0H:ADC0L Register Coding

0xFF : 0xC0

0x80 : 0x00

0x40 : 0x00

0x00 : 0x00

5.4. 8-Bit Compatibility Mode

Setting the ADC08BE bit in register ADC0CF to ‘1’ will put the ADC in 8-bit compatibility mode. This mode

allows backward compatibility with the C8051F300 device family. In 8-bit compatibility mode, only the 8

MSBs of data are converted. The two LSBs of a conversion are always ‘00’ in this mode, and the ADC0L

register will always read back 0x00. 8-bit conversions take two fewer SAR clock cycles than 10-bit conver-

sions, so the conversion is completed faster, and a 500 ksps sampling rate can be achieved with a slower

SAR clock.

32

Rev. 0.5

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