C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The

Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of

100µsec.

Figure 10.15. PCON: Power Control Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

SMOD

GF4

GF3

GF2

GF1

GF0

STOP

IDLE 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x87

Bit7:

SMOD: Serial Port Baud Rate Doubler Enable.

0: Serial Port baud rate is that defined by Serial Port Mode in SCON.

1: Serial Port baud rate is double that defined by Serial Port Mode in SCON.

Bits6-2: GF4-GF0: General Purpose Flags 4-0.

These are general purpose flags for use under software control.

Bit1:

STOP: Stop Mode Select.

Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.

1: Goes into power down mode. (Turns off internal oscillator).

Bit0:

IDLE: Idle Mode Select.

Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.

1: Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial

Ports, and Analog Peripherals are still active.)

Rev. 1.7

86

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