C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 10.12. EIE2: Extended Interrupt Enable 2

R/W

R/W

EXVLD

-

Bit7

Bit6

R/W

EX7

Bit5

R/W

EX6

Bit4

R/W

EX5

Bit3

R/W

EX4

Bit2

R/W

EADC0

Bit1

Bit7:

EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt.

This bit sets the masking of the XTLVLD interrupt.

0: Disable all XTLVLD interrupts.

1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7)

Bit6: Reserved. Must Write 0. Reads 0.

Bit5:

EX7: Enable External Interrupt 7.

This bit sets the masking of External Interrupt 7.

0: Disable External Interrupt 7.

1: Enable interrupt requests generated by the External Interrupt 7 input pin.

Bit4:

EX6: Enable External Interrupt 6.

This bit sets the masking of External Interrupt 6.

0: Disable External Interrupt 6.

1: Enable interrupt requests generated by the External Interrupt 6 input pin.

Bit3:

EX5: Enable External Interrupt 5.

This bit sets the masking of External Interrupt 5.

0: Disable External Interrupt 5.

1: Enable interrupt requests generated by the External Interrupt 5 input pin.

Bit2:

EX4: Enable External Interrupt 4.

This bit sets the masking of External Interrupt 4.

0: Disable External Interrupt 4.

1: Enable interrupt requests generated by the External Interrupt 4 input pin.

Bit1:

EADC0: Enable ADC0 End of Conversion Interrupt.

This bit sets the masking of the ADC0 End of Conversion Interrupt.

0: Disable ADC0 Conversion Interrupt.

1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.

Bit0:

ET3: Enable Timer 3 Interrupt.

This bit sets the masking of the Timer 3 interrupt.

0: Disable all Timer 3 interrupts.

1: Enable interrupt requests generated by the TF3 flag (TMR3CN.7)

R/W

Reset Value

ET3

00000000

Bit0

SFR Address:

0xE 7

Rev. 1.7

82

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