C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 10.11. EIE1: Extended Interrupt Enable 1

R/W

ECP1R

Bit7

R/W

ECP1F

Bit6

R/W

ECP0R

Bit5

R/W

ECP0F

Bit4

R/W

EPCA0

Bit3

R/W

EWADC0

Bit2

R/W

ESMB0

Bit1

Bit7:

ECP1R: Enable Comparator 1 (CP1) Rising Edge Interrupt.

This bit sets the masking of the CP1 interrupt.

0: Disable CP1 Rising Edge interrupt.

1: Enable interrupt requests generated by the CP1RIF flag (CPT1CN.5).

Bit6:

ECP1F: Enable Comparator 1 (CP1) Falling Edge Interrupt.

This bit sets the masking of the CP1 interrupt.

0: Disable CP1 Falling Edge interrupt.

1: Enable interrupt requests generated by the CP1FIF flag (CPT1CN.4).

Bit5:

ECP0R: Enable Comparator 0 (CP0) Rising Edge Interrupt.

This bit sets the masking of the CP0 interrupt.

0: Disable CP0 Rising Edge interrupt.

1: Enable interrupt requests generated by the CP0RIF flag (CPT0CN.5).

Bit4:

ECP0F: Enable Comparator 0 (CP0) Falling Edge Interrupt.

This bit sets the masking of the CP0 interrupt.

0: Disable CP0 Falling Edge interrupt.

1: Enable interrupt requests generated by the CP0FIF flag (CPT0CN.4).

Bit3:

EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.

This bit sets the masking of the PCA0 interrupts.

0: Disable all PCA0 interrupts.

1: Enable interrupt requests generated by PCA0.

Bit2:

EWADC0: Enable Window Comparison ADC0 Interrupt.

This bit sets the masking of ADC0 Window Comparison interrupt.

0: Disable ADC0 Window Comparison Interrupt.

1: Enable Interrupt requests generated by ADC0 Window Comparisons.

Bit1:

ESMB0: Enable SMBus 0 Interrupt.

This bit sets the masking of the SMBus interrupt.

0: Disable all SMBus interrupts.

1: Enable interrupt requests generated by the SI flag (SMB0CN.3).

Bit0:

ESPI0: Enable Serial Peripheral Interface 0 Interrupt.

This bit sets the masking of SPI0 interrupt.

0: Disable all SPI0 interrupts.

1: Enable Interrupt requests generated by SPI0.

R/W

ESPI0

Bit0

Reset Value

00000000

SFR Address:

0xE 6

81

Rev. 1.7

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