ACS411CS View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS411CS Datasheet PDF : 43 Pages
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CSB
ALE = SCLK
A(0) = SDI
AD(0) = SDO
tsu2
tpw2
th2
th1
tpw1
tsu1
R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
Z
Symbol
Parameter
Min
tsu1 Setup SDI valid to SCLK ↑
10 *
tsu2 Setup CSB ↓ to SCLK↑
10 *
th1 Hold SDI to SCLK ↑
10 *
th2 Hold SCLK ↑ to CSB ↑
10 *
tpw1 SCLK low time
240
tpw2 SCLK high time
240
tp
Time between consecutive accesses
(CSB ↑ to CSB ↓ )
250
Typ Max
Figure 11: Write access timing in SERIAL Mode.
Note: preliminary timing information. Timing values marked with * TBA.
uP Interface timing - EPROM mode
In EPROM mode, the ACS4110 takes control of the
bus as master, and reads the device set-up from an
AMD AM27C020 type EPROM at lowest speed
(250ns) after device start-up (system reset). The
EPROM access state machine in the up interface
sequences the accesses. The following figures show
the timing diagrams of the read access for this mode.
For a more detailed timing specification, see AMD
Am27C020 data sheet, July 1993, p. 2-95.
If the microprocessor interface is enabled (UPSEL /
= 0), the default start-up values are taken over from
the pin values as default during reset for the following
control pins:
CM(3:1)
CKC, CKM, TRSEL , RESEL
MSEL(3:1), ENRSB
DR(3:1)
CSB (= OEB)
A
address
tacc
AD
Z
data
Z
Symbol
Parameter
Min Typ Max
tacc Delay CSB ↓ or A change to AD valid -
-
590
Figure 12: Read access timing in EPROM Mode.
Note: preliminary timing information. Timing values marked with * TBA.
21
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
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