CS5376 查看數據表（PDF） - Cirrus Logic

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CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

12.3.2 Decimation Engine Synchronization

The decimation engine uses the rising edge of

MSYNC to reset the FIR filter data pointers. Simi-

lar to the sinc filters, the FIR data pointers are reset

but the data registers themselves are not cleared.

After an MSYNC event the initial output data from

the FIR filters will be a combination of pre-sync

and post-sync data. Valid data is output once all

data registers have been overwritten with new data.

Note that the IIR filters are not directly affected by

a synchronization event, but will require time to

settle due to the FIR filter output discontinuity.

12.3.3 SD Port Synchronization

The serial data output port uses the rising edge of

MSYNC to re-initialize the output data FIFO. Both

the write and read pointers are reset, and the data

registers are cleared. The CS5376 requires one out-

put period to pass after an MSYNC event before

data is available from the SD port.

12.3.4 Time Break Synchronization

The time break function is disabled by a MSYNC

event since MSYNC disturbs filter operations. The

time break timing reference in the output data

stream depends on the group delay of the digital fil-

ters. When a synchronization event occurs, the fil-

ter group delay is no longer consistent which

renders the time break delay invalid.

The rising edge of MSYNC automatically clears

the current time break countdown value and dis-

ables the time break output flag, but does not affect

the programmed counter initialization value in the

TIMEBRK register (0x29).

12.3.5 Test Bit Stream Synchronization

When the test bit stream generator is enabled, the

rising edge of an MSYNC signal resets the TBS

data pointer. This restarts the test bit stream from

the first data point, and establishes a known phase

in the output signal.

In the internal test bit stream data set, the first data

point is the initial positive going data value of a

1024 point sine wave. An MSYNC event will

therefore restart the test bit stream generator at zero

degrees phase when using the internal data set.

The first data value of a custom test bit stream data

set can be defined to be anywhere in the test signal.

This permits setting the test bit stream generator

output phase by defining the first data point to be a

non-zero degree phase of the test signal.

12.4 Modulator Synchronization

The generated MSYNC signal is used internally to

synchronize the CS5376, but is also output to the

MSYNC pin to phase align the modulator sam-

pling. Since high precision modulators such as the

CS5372 require multiple MCLK phases to com-

plete a conversion, unsynchronized modulators can

have random sampling instants relative to each oth-

er. The MSYNC signal guarantees all modulators

in a network have the same sampling instant.

DS256PP1

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