CS5376 查看數據表（PDF） - Cirrus Logic

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CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

The characteristic equation for FIR2 is a convolu-

tion of the input values, X(n), and the filter coeffi-

cients, h(k), to produce an output value, Y.

Y = [h(k)*X(n-k)] + [h(k+1)*X(n-(k+1))] + ...

8.3.3 Maximum FIR Coefficients

The maximum number of 255 coefficients can not

be used simultaneously for both FIR1 and FIR2.

The large maximum size for the FIR filters is in-

tended for applications that require only one FIR

filter, or require two FIR filters consisting of a sim-

ple filter combined with a more complex filter. The

total number of FIR coefficients that can be used

depends on the selected decimation engine internal

clock rate, the number of enabled conversion chan-

nels, and if the IIR filters are enabled.

8.3.4 FIR Coefficient Upload

Custom FIR coefficients are uploaded through the

SPI 1 serial port using the ‘Write FIR Coefficients’

command to perform a burst write of both the FIR1

and FIR2 coefficients. See “Serial Peripheral Inter-

face 1” on page 21 for information about how to

upload custom FIR coefficients.

8.3.5 FIR Filter Synchronization

The FIR1 and FIR2 filters are synchronized to the

external system by the MSYNC signal, which is

generated from the SYNC input. The MSYNC sig-

nal sets a reference time (time 0) for all filter oper-

ations, and the FIR filters are restarted to phase

align with this reference time. See “System Syn-

chronization” on page 77 for information about

how the MSYNC signal is generated.

During synchronization, the FIR filters reset all in-

ternal address pointers and restart the filter on the

next data input. Existing data in the internal data

registers is not cleared, so immediately after syn-

chronization the data from the FIR filters will be a

combination of pre-sync and post-sync data.

8.4 IIR Filter

The infinite impulse response (IIR) filter is a select-

able 1st, 2nd, or 3rd order filter with programmable

coefficients. The IIR filter architecture is multi-

stage with cascaded 1st order and 2nd order filters,

as shown in Figure 39.

The structure of the IIR filter is automatically de-

termined when the output filter stage is selected in

the FILT_CFG register. Selection of a 1st order IIR

1st Order IIR

b10

Z-1

-a11

b11

3rd Order IIR implemented

by running both stages

2nd Order IIR

b20

Z-1

-a21

b21

Z-1

-a22

b22

Figure 39. IIR Filters

DS256PP1

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