CLK
T0 T1 T2 T3 T4
CKE
nCS
all
nRAS /
nCAS / nWE
NOP REF NOP NOP NOP (ACT)
tRP
tRC1
auto precharge
DQM
DQ
Bank sel
A10
(prech sel)
addr
Figure 30. SDRAM Refresh Cycles
CL[2]
CL[1]
FRM
M
DD[3:0]
t20
t15
t16
t17
t18
t19
t21
t22
t23
Notes: 1. The figure shows the end of a line.
2. If FRM is high during the CL[1] pulse, this marks the first line in the display.
3. CL[2] low time is doubled during the CL[1] high pulse
Figure 31. LCD Controller Timings
CS89712
DS502PP2
157