CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

CLK

CKE

nCS

nRAS /

nCAS / nWE

DQM

DQ

Bank sel

A10

(prech sel)

addr

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

1 dev

1 dev

CAS lat 2

NOP ACT NOP READ NOP NOP NOP NOP NOP NOP NOP (ACT)

tRCD

tRAS

tRC

tRP

auto precharge

bank

bank

row

row

col

DI0 DI1 DI2 DI3

1. tRCD (delay time ACT to READ/WRITE command) = 30 ns or 2 cycles at 36 MHz.

2. tRP (PRE to ACT command period) = 30 ns or 2 cycles at 36 MHz.

3. tRAS (ACT to PRE command period) = 60 ns or 3 cycles at 36 MHz.

4. tRC (ACT to REF/ACT command period [operation]) = 90 ns or 4 cycles at 36 MHz.

5. For SDCAS latency 3, there will be an extra cycle between T4 and T5.

6. For CAS latency 3, there will be an extra cycle between T4 and T5.

Figure 27. SDRAM Read Cycles CAS Latency = 2

DS502PP2

155

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