LTC695C-3.3 查看數據表（PDF） - Linear Technology
零件编号
产品描述 (功能)
生产厂家
LTC695C-3.3 Datasheet PDF : 20 Pages
| |||
LTC694-3.3/LTC695-3.3
APPLICATIONS INFORMATION
VCC = 3.3V
WDI
WDO
RESET
t1 = RESET ACTIVE TIME
t2 = NORMAL WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY
AFTER A RESET
t2
t3
t1
t1
Figure 11. Watchdog Timeout Period and Reset Active Time
694/5-3.3 F11
EXTERNAL CLOCK
3.3V
3
VCC
OSC SEL 8
LTC695-3.3
4
GND
7
OSC IN
EXTERNAL OSCILLATOR
3.3V 3 VCC
8
OSC SEL
LTC695-3.3
4
GND
7
OSC IN
INTERNAL OSCILLATOR
1.6 SECOND WATCHDOG
3.3V 3 VCC
8
OSC SEL
FLOATING
OR HIGH
LTC695-3.3
4
GND
7
OSC IN
FLOATING
OR HIGH
INTERNAL OSCILLATOR
100ms WATCHDOG
3
3.3V
VCC
OSC SEL 8
FLOATING
OR HIGH
LTC695-3.3
4
GND
OSC IN 7
Figure 12. Oscillator Configurations
694/5-3.3 F12
WDI pin remains either high or low, reset pulses will be
issued every 1.6 seconds typically. The watchdog time
can be deactivated by floating the WDI pin. The timer
is also disabled when VCC falls below the reset voltage
threshold or VBATT.
The LTC695-3.3 provides an additional output (Watchdog
Output, WDO) which goes low if the watchdog timer is
allowed to time out and remains low until set high by the
next transition on the WDI pin. WDO is also set high when
VCC falls below the reset voltage threshold or VBATT.
14
The LTC695-3.3 has two additional pins, OSC SEL and OSC
IN, which allow reset active time and watchdog timeout
period to be adjusted per Table 2. Several configurations
are shown in Figure 12.
OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and
GND when OSC SEL is forced low. In these configura-
tions, the nominal reset active time and watchdog timeout
period are determined by the number of clocks or set by
the formula in Table 2. When OSC SEL is high or floating,
69453fb
Share Link: 