LTC695C-3.3 查看數據表（PDF） - Linear Technology

零件编号

产品描述 (功能)

生产厂家

LTC695C-3.3

3.3V Microprocessor Supervisory Circuits

Linear Technology 

LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

3.3V

0.1μF

2.4V

VCC

VOUT +

LTC695-3.3

CE OUT

VBATT

GND

CE IN

RESET

RESET

10μF

0.1μF

30ns PROPAGATION DELAY

FROM DECODER

VCC

62512

RAM

CSGND

TO μP

694/5-3.3 F06

Figure 6. A Typical Nonvolatile CMOS RAM Application

3.3V

0.1μF

2.4V

VCC

VOUT +

10μF

LTC694-3.3

VBATT RESET

GND

0.1μF

CS

VCC

62128

RAM

CS1

CS2

GND

694/5-3.3 F07

Figure 7. Write Protect for RAM with LTC694-3.3

VIN ≥ 5V

+

R1

51k

10μF

LT1129-3.3

VIN VOUT

OUT SENSE

SHDN

ADJ

R2

16k

3.3V

+

100μF 0.1μF

R3

200k

R4

10k

VCC

LTC694-3.3

LTC695-3.3

PFO

PFI GND

TO μP

694/5-3.3 F08

Figure 8. Monitoring Unregulated DC Supply with the

LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

VIN r 6.5V

+

10μF

LT1129-3.3

VIN VOUT

OUT SENSE

SHDN

ADJ

10μF

+

3.3V

R1 R4

27k 10k

R3

2.7M

R2

16k

R5

5k

0.1μF

VCC

LTC694-3.3

LTC695-3.3

PFO

PFI GND

694/5-3.3 F09

TO μP

CE IN can be derived from the microprocessor’s address

decoder output. Figure 6 shows a typical nonvolatile CMOS

RAM application.

Memory protection can also be achieved with the LTC694-

3.3 by using RESET as shown in Figure 7.

Power-Fail Warning

The LTC694-3.3/LTC695-3.3 generate a Power Failure Out-

put (PFO) for early warning of failure in the microprocessor’s

power supply. This is accomplished by comparing the

power failure input (PFI) with an internal 1.3V reference.

PFO goes low when the voltage at the PFI pin is less than

1.3V. Typically PFI is driven by an external voltage divider

(R1 and R2 in Figures 8 and 9) which senses either an

unregulated DC input or a regulated 3.3V output. The

voltage divider ratio can be chosen such that the voltage

at the PFI pin falls below 1.3V several milliseconds before

the 3.3V supply falls below the maximum reset voltage

threshold 3.0V. PFO is normally used to interrupt the

microprocessor to execute shutdown procedure between

PFO and RESET or RESET.

The power-fail comparator, C3, does not have hysteresis.

Hysteresis can be added however, by connecting a resistor

between the PFO output and the noninverting PFI input

pin as shown in Figures 8 and 9. The upper and lower trip

points in the comparator are established as follows:

When PFO output is low, R3 sinks current from the sum-

ming junction at the PFI pin.

VH

=1.3V

⎛

⎝⎜

1+

R1

R2

+

R1⎞

R3 ⎠⎟

When PFO output is high, the series combination of R3

and R4 source current into the PFI summing junction.

VL

=

1.3V

⎛⎝⎜1+

R1

R2

–

(3.3V ±1.3V)R1⎞

1.3V(R3 + R4) ⎠⎟

Assuming

R4

<<

R3,

VHYSTERESIS

=

3.3V

R1

R3

Figure 9. Monitoring Regulated DC Supply with the

LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

69453fb

12

Share Link: