SI5328C-C-GM 查看數據表（PDF） - Silicon Laboratories

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SI5328C-C-GM

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Register 128.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

CK2_ACTV_REG CK1_ACTV_REG

Type

R

R

R

Reset value = 0010 0000

Bit

Name

Function

7:2

Reserved Reserved.

1 CK2_ACTV_REG CK2_ACTV_REG.

Indicates if CKIN2 is currently the active clock for the PLL input.

0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.

1: CKIN2 is the active input clock.

0 CK1_ACTV_REG CK1_ACTV_REG.

Indicates if CKIN1 is currently the active clock for the PLL input.

0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.

1: CKIN1 is the active input clock.

48

Rev. 1.0

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