NXP Semiconductors
PCA8538
Automotive 102 x 9 Chip-On-Glass LCD segment driver
8.14.2.4 RAM filling in 1:6 multiplex drive mode
In the 1:6 multiplex drive mode the eight transmitted data bits are placed as shown in
Table 43.
Table 43. RAM filling in 1:6 multiplex drive mode
RAM row/ RAM column/Segment output (S)
backplane 0
1
2
3
:
output
(COM)
0
aa7
aa1
ab3
ac5
:
1
aa6
aa0
ab2
ac4
:
2
aa5
ab7
ab1
ac3
:
3
aa4
ab6
ab0
ac2
:
4
aa3
ab5
ac7
ac1
:
5
aa2
ab4
ac6
ac0
:
6
-
-
-
-
:
7
-
-
-
-
:
8
-
-
-
-
:
99
100
101
cw5
cx7
cx1
cw4
cx6
cx0
cw3
cx5
cy7
cw2
cx4
cy6
cw1
cx3
cy5
cw0
cx2
cy4
-
-
-
-
-
-
-
-
-
The remaining bits of a byte are wrapped up into the next column. In order to fill the whole
RAM addresses 77 bytes need to be sent to the PCA8538. Any data bits that spill over the
RAM and additional data bytes sent are discarded.
8.14.2.5 RAM filling in 1:8 multiplex drive mode
In the 1:8 multiplex drive mode the eight transmitted data bits are placed into eight rows of
one display RAM column (see Table 44).
Table 44. RAM filling in 1:8 multiplex drive mode
RAM row/
backplane
output
(COM)
RAM column/Segment output (S)
0
1
2
:
0
aa7
ab7
ac7
:
1
aa6
ab6
ac6
:
2
aa5
ab5
ac5
:
3
aa4
ab4
ac4
:
4
aa3
ab3
ac3
:
5
aa2
ab2
ac2
:
6
aa1
ab1
ac1
:
7
aa0
ab0
ac0
:
8
-
-
-
:
99
100
101
dv7
dw7
dx7
dv6
dw6
dx6
dv5
dw5
dx5
dv4
dw4
dx4
dv3
dw3
dx3
dv2
dw2
dx2
dv1
dw1
dx1
dv0
dw0
dx0
-
-
-
In order to fill the whole RAM addresses 102 bytes need to be sent to the PCA8538.
Additional data bytes sent are discarded.
8.14.2.6 RAM filling in 1:9 multiplex drive mode
In the 1:9 multiplex drive mode the transmitted bytes are stored continuously in the eight
RAM rows until RAM column 101 while the data pointer X is automatically wrapped
around from RAM column 0 to RAM column 101 (data pointer Y remains logic 0). Then the
PCA8538
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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