CS8415A-CS 查看數據表（PDF） - Cirrus Logic

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CS8415A-CS

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

9. PIN DESCRIPTION - SOFTWARE MODE

SDA/CDOUT 1

AD0/CS 2

EMPH 3*+

RXP0 4*

RXN0 5*

VA+ 6*

AGND 7*

FILT 8*

RST 9*

RMCK 10*

RERR 11*

RXP1 12

RXP2 13

RXP3 14

28 SCL/CCLK

27 AD1/CDIN

26 RXP6

25 RXP5

*24 H/S

*23 VL+

*22 DGND

*21 OMCK

20 U

19 INT

*18 SDOUT

*17 OLRCK

*16 OSCLK

15 RXP4

* Pins which remain the same function in all modes.

+ Pins which require a pull up or pull down resistor

to select the desired startup option.

CS8415A

Pin Name

SDA/CDOUT

AD0/CS

EMPH

RXP0

RXN0

RXP1

RXP2

RXP4

RXP6

RXP3

RXP5

VA+

# Pin Description

Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C mode, SDA is the control I/O data

1 line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the out-

put data from the control port interface on the CS8415A

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the

2

CS8415A into SPI control port mode. With no falling edge, the CS8415A defaults to I²C mode. In I²C

mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the

CS8415A

Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 ms

3

pre-emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-

emphasis other than 50/15 ms. This is also a start-up option pin, and requires a 47 kΩ resistor to either

VL+ or DGND, which determines the AD2 address bit for the control port in I²C mode

4

5

AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs carrying AES3 data. RXP0 may be

used as a single-ended input as part of 7:1 S/PDIF Input MUX. If RXP0 is used in MUX, RXN0 must be

ac coupled to ground.

12

13 Additional AES3/SPDIF Receiver Port (Input) - Single-ended receiver inputs carrying AES3 or S/PDIF

14 digital data. These inputs, along with RXP0, comprise the 7:1 S/PDIF Input Multiplexer and select line

15 control is accessed using the MUX2:0 bits in the Control 2 register. Please note that any unused inputs

25 should be tied to ground. See Appendix A for recommended input circuits.

26

Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5.0 V. This supply

6 should be as quiet as possible since noise on this pin will directly affect the jitter performance of the

recovered clock

30

DS470F4

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