CS8415A-CS 查看數據表（PDF） - Cirrus Logic

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CS8415A-CS

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

8.15 User Data Buffer Control (13h)

7

6

5

4

3

0

0

0

0

0

DETUI - D to E U-data buffer transfer inhibit bit.

Default = ‘0’

0 - Allow U-data D to E buffer transfers

1 - Inhibit U-data D to E buffer transfers

CS8415A

2

1

0

0

DETUI

0

8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)

The following 10 registers contain the decoded Q-channel subcode data

7

6

5

4

3

2

1

0

CONTROL CONTROL CONTROL CONTROL ADDRESS ADDRESS ADDRESS ADDRESS

TRACK

TRACK

TRACK

TRACK

TRACK

TRACK

TRACK

TRACK

INDEX

INDEX

INDEX

INDEX

INDEX

INDEX

INDEX

INDEX

MINUTE

MINUTE

MINUTE

MINUTE

MINUTE

MINUTE

MINUTE

MINUTE

SECOND

SECOND

SECOND

SECOND

SECOND

SECOND

SECOND

SECOND

FRAME

FRAME

FRAME

FRAME

FRAME

FRAME

FRAME

FRAME

ZERO

ZERO

ZERO

ZERO

ZERO

ZERO

ZERO

ZERO

ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE

ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND

ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0] while

bit 0 of address 0Eh is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79].

8.17 OMCK/RMCK Ratio (1Eh) (Read Only)

7

ORR7

6

ORR6

5

ORR5

4

ORR4

3

ORR3

2

ORR2

1

ORR1

0

ORR0

This register allows the calculation of the incoming sample rate by the host microcontroller from the equation

ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256 Fso. ORR is rep-

resented as an unsigned 2-bit integer and a 6-bit fractional part. The value is meaningful only after the PLL

has reached lock. For example, if the OMCK is 12.288 MHz, Fso would be 48 kHz (48 kHz =

12.288 MHz/256). Then if the input sample rate is also 48 kHz, you would get 1.0 from the ORR regis-

ter.(The value from the ORR register is hexadecimal, so the actual value you will get is 40h). If FSO/FSI > 3

63/64, ORR will saturate at the value FFh. Also, there is no hysteresis on ORR. Therefore a small amount of

jitter on either clock can cause the LSB ORR[0] to oscillate.

ORR7:6 - Integer part of the ratio (Integer value=Integer(SRR[7:6]))

ORR5:0 - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)

8.18 C-bit or U-bit Data Buffer (20h - 37h)

Either channel status data buffer E or user data buffer E is accessible through these register addresses.

28

DS470F4

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