CS8415A-CS 查看數據表（PDF） - Cirrus Logic

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CS8415A-CS

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8415A

ORIG - SCMS generation indicator, decoded from the category code and the L bit.

0 - Received data is 1st generation or higher

1 - Received data is original

Note: COPY and ORIG will both be set to 1 if the incoming data is flagged as professional, or if the re-

ceiver is not in use.

8.12 Receiver Error (10h) (Read Only)

7

6

5

4

3

2

1

0

0

QCRC

CCRC

UNLOCK

V

CONF

BIP

PAR

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of

the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error

source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register.

This register defaults to 00h.

QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries

0 - No error

1 - Error

CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid in Pro

mode

0 - No error

1 - Error

UNLOCK - PLL lock status bit. Updated on CS block boundaries.

0 - PLL locked

1 - PLL out of lock

V - Received AES3 Validity bit status. Updated on sub-frame boundaries.

0 - Data is valid and is normally linear coded PCM audio

1 - Data is invalid, or may be valid compressed audio

CONF - Confidence bit. Updated on sub-frame boundaries.

0 - No error

1 - Confidence error. This is the logical OR of BIP and UNLOCK.

BIP - Bi-phase error bit. Updated on sub-frame boundaries.

0 - No error

1 - Bi-phase error. This indicates an error in the received bi-phase coding.

PAR - Parity bit. Updated on sub-frame boundaries.

0 - No error

1 - Parity error

26

DS470F4

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