CS61305A 查看數據表（PDF） - Cirrus Logic

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CS61305A

T1/E1 Line Interface

Cirrus Logic 

CS61305A

Parameter

Turns Ratio

Receiver

1:2 CT ± 5%

Primary Inductance

Primary Leakage Inductance

Secondary Leakage Inductance

Interwinding Capacitance

ET-constant

600 µH min. @ 772 kHz

1.3 µH max. @ 772 kHz

0.4 µH max. @ 772 kHz

23 pF max.

16 V-µs min. for T1

12 V-µs min. for E1

Table A2. Transformer Specifications

Transmitter

1:1 ± 1.5 % for 75 Ω E1

1:1.15 ± 5 % for 100 Ω T1

1:1.26 ± 1.5 % for 120 Ω E1

1.5 mH min. @ 772 kHz

0.3 µH max. @ 772 kHz

0.4 µH max. @ 772 kHz

18 pF max.

16 V-µs min. for T1

12 V-µs min. for E1

Interfacing The CS61305A With the

CS62180B T1 Transceiver

To interface with the CS62180B, connect the de-

vices as shown in Figure A5. In this case, the line

interface and CS62180B are in Host mode con-

trolled by a microprocessor serial interface. If the

line interface is used in Hardware mode, then the

line interface RCLK output must be inverted be-

fore being input to the CS62180B. If the

CS61305A is used in Extended Hardware Mode,

the RCLK output does not have to be inverted

before being input to the CS62180B.

TO HOST CONTROLLER

SCLK

SDO

SDI

CS

TCLK

TPOS

TNEG

1.544 MHz

CLOCK

SIGNAL

RNEG

RPOS

RCLK

CS62180B

ACLK

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

SCLK

SDO

SDI

CS

INT

CLKE

MODE

CS61305A

V+

100k

22k V+

Figure A5. Interfacing the CS61305A with a

CS62180B (Host Mode)

28

DS157PP3

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