CS61305A 查看數據表（PDF） - Cirrus Logic

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CS61305A

T1/E1 Line Interface

Cirrus Logic 

CS61305A

SDO - Serial Data Output, Pin 25. (Host Mode)

Status and control output from the output data register. If CLKE is high SDO is valid on the

rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to

a high-impedance state when the serial port is being written, or if CS is high, or after bit D7 is

output.

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)

Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined

by ACLKI.

TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)

Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting

TCODE high enables the AMI transmitter encoder .

Data

RCLK - Recovered Clock, Pin 8.

The receiver recovered clock is output on this pin.

RDATA - Receive Data - Pin 7. (Extended Hardware Mode)

Data recovered from the RTIP and RRING inputs is output in NRZ format at this pin, after being

decoded by the line code decoder. RDATA is stable and valid on the falling edge of RCLK.

RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and

Host Modes)

The receiver recovered NRZ digital data from RTIP and RRING is output on these pins. A

positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS,

and a positive pulse (with respect to ground) received on the RRING pin generates a logic 1 on

RNEG. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of

RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are

stable and valid (see Table 5).

RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.

The AMI receive signal is input on these pins. A center-tapped, center-grounded, 2:1, step-up

transformer is required on these inputs, as shown in Figure A1 of the Applications section. Clock

and data are recovered and output on RCLK and RPOS/RNEG or RDATA.

TCLK - Transmit Clock, Pin 2.

The1.544 MHz (T1 operation) or 2.048 MHz (E1 operation) transmit clock is input on this pin.

TPOS/TNEG or TDATA are sampled on the falling edge of TCLK.

TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)

Data to be transmitted by the TTIP and TRING outputs is input in NRZ format at this pin, after

being encoded by the line code encoder. TDATA is sampled on the falling edge of TCLK.

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DS157PP3

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