CS61305A 查看數據表（PDF） - Cirrus Logic

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CS61305A

T1/E1 Line Interface

Cirrus Logic 

CS61305A

1) The current interrupt on the serial interface

will be cleared. (Note that simply reading

the register bits will not clear the inter-

rupt).

2) Output data bits D5, D6 and D7 will be re-

set as appropriate.

3) Future interrupts for the corresponding LOS

or DPM will be prevented from occurring.

Writing a "0" to either "Clear LOS" or "Clear

DPM" enables the corresponding interrupt for

LOS or DPM.

Bit Designation

Description

D0

LOS

Loss of Signal

D1

DPM

Driver Performance Monitor

D2

LEN0

Bit 0 - Line Length Select

D3

LEN1

Bit 1 - Line Length Select

D4

LEN2

Bit 2 - Line Lenght Select

Note: Bit D0 is the first bit output (LSB)

Table 11. Output Data Register (bits D0-D4)

During a read cycle (R/W = 1), data is read from

the output data register on the eight clock cycles

immediately following the address/ command

byte. The output data format over SDO is shown

in Tables 11 and 12.

Bits D2, D3 and D4 can be read to verify line

length selection. Bits D5, D6 and D7 must be de-

coded according to Table 12. Codes 101, 110 and

111 (Bits D5, D6 and D7) indicate intermittent

losses of signal and/or driver problems.

Bits

D5 D6 D7

Status

0 0 0 Reset has occurred or no program input.

0 0 1 TAOS in effect.

0 1 0 LLOOP in effect.

0 1 1 TAOS/LLOOP in effect.

1 0 0 RLOOP in effect

1 0 1 DPM changed state since last "clear DPM"

occured.

1 1 0 LOS changed state since last "clear LOS"

occured.

1 1 1 LOS and DPM have changed state since

last "clear LOS" and "clear DPM".

Table 12. Output Data Register (bits D5-D7)

respective grounds. TV+ must not exceed RV+ by

more than 0.3V.

Decoupling and filtering of the power supplies is

crucial for the proper operation of the analog cir-

cuits in both the transmit and receive paths. A 1.0

µF capacitor should be connected between TV+

and TGND, and a 0.1 µF capacitor should be con-

nected between RV+ and RGND. Use mylar or

ceramic capacitors and place them as closely as

possible to their respective power supply pins. A

68 µF tantalum capacitor should be added close

to the RV+/RGND supply. Wire-wrap bread-

boarding of the line interface is not recommended

because lead resistance and inductance serve to

defeat the function of the decoupling capacitors.

The SDO pin goes to a high impedance state

when not in use. The SDO and SDI pins may be

tied together in applications where the host proc-

essor has a bi-directional I/O port.

Power Supply

The device operates from a single +5 Volt supply.

Separate pins for transmit (TV+, TGND) and re-

ceive (RV+, RGND) supplies provide internal

isolation. These pins should be connected exter-

nally near the device and decoupled to their

18

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Schematic & Layout

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