CS61305A 查看數據表（PDF） - Cirrus Logic

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CS61305A

T1/E1 Line Interface

Cirrus Logic 

CS61305A

CS

SCLK

SDI

SDO

R/W 0 0 0 0 1 0 X D0 D1 D2 D3 D4 D5 D6 D7

Address/Command Byte

Data Input/Output

D0 D1 D2 D3 D4 D5 D6 D7

Figure 13. Input/Output Timing

host controller can be used to control operational

characteristics and monitor device status. The se-

rial port read/write timing is independent of the

system transmit and receive timing.

Data transfers are initiated by taking the chip se-

lect input, CS, low (CS must initially be high).

Address and input data bits are clocked in on the

rising edge of SCLK. The clock edge on which

output data is stable and valid is determined by

CLKE as shown in Table 5. Data transfers are ter-

minated by setting CS high. CS may go high no

sooner than 50 ns after the rising edge of the

SCLK cycle corresponding to the last write bit.

For a serial data read, CS may go high any time

to terminate the output.

Figure 13 shows the timing relationships for data

transfers when CLKE = 1. When CLKE = 1, data

bit D7 is held until the falling edge of the 16th

clock cycle. When CLKE = 0, data bit D7 is held

until the rising edge of the 17th clock cycle. SDO

goes to the high impedance state when the serial

port is being written (R/W = 0), or if CS goes

high, or at the end of the hold period of data bit

D7.

An address/command byte, shown in Table 9,

precedes the data byte. The first bit of the ad-

dress/command byte determines whether a read

or a write is requested. The next six bits contain

the address. The line interface responds to address

16 (0010000). The last bit is ignored.

Bit Designation

Description

0

R/W

Read/Write Select; 0 = write, 1 = read

1

ADD0

LSB of address, Must be 0

2

ADD1

Must be 0

3

ADD2

Must be 0

4

ADD3

Must be 0

5

ADD4

Must be 1

6

-

Reserved - Must be 0

7

X

Don’t Care

Note: Bit 0 is the first bit input (LSB).

Table 9. Address/Command Byte

During a write cycle (R/W = 0), data is written to

the input data register on the eight clock cycles

immediately following the address/command

byte. The input data format over SDI is shown in

Table 10.

Bit Designation

Description

D0

clr LOS

Clear Loss of Signal

D1

clr DPM

Clear Driver Performance Monitor

D2

LEN0

Bit 0 - Line Length Select

D3

LEN1

Bit 1 - Line Length Select

D4

LEN2

Bit 2 - Line Lenght Select

D5

RLOOP

Remote Loopback

D6

LLOOP

Local Loopback

D7

TAOS

Transmit All Ones Select

Note: Bit D0 is the first bit input (LSB).

Table 10. Input Data Register

Bits D0 and D1 are used to clear an interrupt is-

sued from the INT pin, which occurs in response

to a loss of signal or a problem with the output

driver.

DS157PP3

Writing a "1" to either "Clear LOS" or "Clear

DPM" over the serial interface has three effects:

17

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