CS61305A 查看數據表（PDF） - Cirrus Logic

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CS61305A

T1/E1 Line Interface

Cirrus Logic 

RTIP

1:2

RRING

Data

Level

Slicer

Edge

Detector

Data

Sampling

&

Clock

Extraction

Clock

Phase

Selector

CS61305A

RPOS

RNEG

RCLK

Continuously

Calibrated

Delay Line

ACLKI or

Oscillator in Jitter

Attenuator

Figure 11. Receiver Block Diagram

put from the phase selector feeds the clock and

data recovery circuits which generate the recov-

ered clock and sample the incoming signal at

appropriate intervals to recover the data. The jitter

tolerance of the receiver exceeds that shown in

Figure 12.

The CS61305A outputs a clock immediately upon

power-up and will lock onto the AMI data input

immediately. If loss of signal occurs, the RCLK

frequency will equal the ACLKI frequency.

In the Hardware Mode, data at RPOS and RNEG

is stable and may be sampled on the rising edge

of the recovered clock. In the Extended Hardware

Mode, data at RDATA is stable and may be sam-

pled on the fallings edge of the recovered clock.

In the Host Mode, CLKE determines the clock

polarity for which output data is stable and valid

as shown in Table 5.

Jitter and Recovered Clock

The CS61305A is designed for error free clock

and data recovery from an AMI encoded data

300

138

100

28

10

PEAK-TO-PEAK

JITTER

(unit intervals)

1

.4

.1

1

Minimum

Performance

AT&T 62411

10

100 300 700 1k

10k

JITTER FREQUENCY

(Hz)

100k

Figure 12. Minimum Input Jitter Tolerance of Receiver

MODE

(pin 5)

CLKE DATA CLOCK Clock Edge

(pin 28)

for Valid Data

LOW

(<0.2V)

X

RPOS RCLK

Rising

RNEG RCLK

Rising

HIGH

LOW

(>(V+) - 0.2V)

RPOS

RNEG

SDO

RCLK

RCLK

SCLK

Rising

Rising

Falling

HIGH

HIGH

(>(V+) - 0.2V)

RPOS

RNEG

SDO

RCLK

RCLK

SCLK

Falling

Falling

Rising

MIDDLE

(2.5V)

X RDATA RCLK

Falling

X = Don’t care

Table 5. Data Output/Clock Relationship

DS157PP3

13

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