CS7620-IQ 查看數據表（PDF） - Cirrus Logic
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CS7620-IQ Datasheet PDF : 70 Pages
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CS7620
4.30 Horizontal Timing Control - H1
Default = 68h; Read/Write (address 29h)
Bit Number
Bit Name
Default
7
6
5
Reserved
h1d
h1f_reg2
-
1
1
4
h1f_reg1
0
3
h1f_reg0
1
2
h1f_reg2
0
1
h1f_reg1
0
0
h1f_reg0
0
Bit
Mnemonic
Function
7
-
Reserved
H1 Default Setting: During the vertical shift time, the horizontal clocks are
held in one state. This bit controls whether H1 is held high or low during this
6
h1d
time.
A “0” indicates that the signal state is low, a “1” indicates that the signal state
is high.
H1 Falling Edge: The phase of the falling edge of H1 can be programmed
through this register. The falling edge of H1 corresponds to the rising edge of
5
h1f_reg2
the internally selected clock. The phases of these clocks are shown in Figure
19, with the complemented clocks being the inverse of these.
4
h1f_reg1
3
h1f_reg0
0 = t0
1 = t1
2 = t2
3 = t3
4 = t4
5 = t5
6 = t6
7 = t7
(See Figure 19)
H1 Rising Edge: The phase of the rising edge of H1 can be programmed
through this register. The rising edge of H1 corresponds to the rising edge of
2
h1f_reg2
the internally selected clock. The phases of these clocks are shown in Figure
19, with the complemented clocks being the inverse of these.
1
h1f_reg1
0
h1f_reg0
0 = t0
1 = t1
2 = t2
3 = t3
4 = t4
5 = t5
6 = t6
7 = t7
(See Figure 19)
48
DS301PP2
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