CS7620-IQ 查看數據表（PDF） - Cirrus Logic
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CS7620-IQ Datasheet PDF : 70 Pages
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CS7620
4.20 Timing Control - Number of Rows until Active
Default = C6h; Read/Write (address 1Eh)
Bit Number
Bit Name
Default
7
6
5
4
3
2
1
0
act_rws_frst3 act_rws_frst2 act_rws_frst1 act_rws_frst0 act_rws_lst3 act_rws_lst2 act_rws_lst1 act_rws_lst0
1
1
0
0
0
1
1
0
Bit
Mnemonic
Function
Active Rows: act_rws_frst corresponds to the first group of non active rows
7
act_rws_frst3
at the top of the image, which get inverted through the lens, and get focused
onto the bottom rows of the CCD.
6
act_rws_frst2
The register value is used by the CS7620 when the part is in the valid data
mode to generate the data valid signal on the CLKO pin.
5
act_rws_frst1
Valid data can be set through the above mentioned registers together with
act_begin(1Fh) to define a subset of pixels to be passed to the subsequent
4
act_rws_frst0
ASIC or DSP component. This subset may or may not include dark rows
and/or dark pixels. Please refer to Figure 28.
Active Rows: act_rws_lst corresponds to the last group of non active rows at
3
act_rws_lst3
the bottom of the image, which get inverted through the lens, and get focused
onto the top rows of the CCD.
2
act_rws_lst2
The register value is used by the CS7620 when the part is in the valid data
mode to generate the data valid signal on the CLKO pin.
1
act_rws_lst1
Valid data can be set through the above mentioned registers together with
act_begin(1Fh) to define a subset of pixels to be passed to the subsequent
0
act_rws_lst0
ASIC or DSP component. This subset may or may not include dark rows
and/or dark pixels. Please refer to Figure 28.
blk_end (1Dh)
blk_begin (1Ch)
drk_rws_lst (1Bh)
act_rws_lst (1Eh)
Dark Pixels
num_lines (17h, 18h)
DS301PP2
ACTIVE PIXELS
num_pixels (19h, 1Ah)
drk_rws_frst (1Bh)
act_rws_frst (1Eh)
shiftl_num (21h, 22h)
TRANSFER
AREA
Figure 28. Typical CCD Pixel Arrangement
41
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