CS7620-IQ 查看數據表（PDF） - Cirrus Logic

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CS7620-IQ

CCD Imager Analog Processor

Cirrus Logic 

CS7620

4.21 Timing Control - Start of Active Pixels

Default = 4Bh; Read/Write (address 1Fh)

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

act_begin7 act_begin6 act_begin5 act_begin4 act_begin3 act_begin2 act_begin1 act_begin0

0

1

0

0

1

0

1

1

Bit

Mnemonic

Function

7

act_begin7

Active Pixels: This register should be programmed with the pixel number of

the first active pixel to be read out. That is the first pixel after the extra pixels,

6

act_begin6

the black pixels, and the grey pixel.

5

act_begin5

This register value is used by the CS7620 when the part is in the valid data

4

act_begin4

mode to generate the data valid signal on the CLKO pin.

3

act_begin3

Valid data can be set through the above mentioned registers together with

act_begin(1Fh) to define a subset of pixels to be passed to the subsequent

2

act_begin2

ASIC or DSP component. This subset may or may not include dark rows

1

act_begin1

and/or dark pixels. Please refer to Figure 28.

The default value is set to 75, which is the sum of the blk_end register (1Dh)

0

act_begin0

and act_rws_lst register (1Eh).

4.22 Timing Control - Vertical Time Division

Default = 01h; Read/Write (address 20h)

Bit Number

Bit Name

Default

7

6

5

Reserved

-

-

-

4

3

2

1

0

tdv4

tdv3

tdv2

tdv1

tdv0

0

0

0

0

1

Bit

Mnemonic

Function

7:5

-

Reserved

4

tdv4

Critical Timing: This determines the width of the minimum vertical division

3

tdv3

measured in pixel clocks. (One vertical pixel shift (row) requires 8 vertical time

2

tdv2

division slots) See Figure 33.

1

tdv1

0

tdv0

42

DS301PP2

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