CS5464-IS 查看數據表（PDF） - Cirrus Logic

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CS5464-IS

Three-channel, Single-phase Power/Energy IC

Cirrus Logic 

CS5464

E3MODE1:0

POS

AFC

E3 Output Mode

00 = Reactive Power (default)

01 = PFMON

10 = Voltage sign

11 = Apparent Power

Positive Energy Only. Negative energy pulses on E1 are suppressed. However, negative P reg-

ister results will NOT be suppressed.

Enables automatic line frequency measurement and sets the frequency of the local sine/cosine

generator used in fundamental/harmonic measurements. When AFC is enabled, the Epsilon

register will be updated periodically.

6.2.7 Epsilon (ε) Register

Address: 17

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default = 0x01999A = 0.0125 sec

Epsilon (ε) is the ratio of the input line frequency to the sample frequency of the ADC (See Section 5.4 Perform-

ing Measurements on page 17). Epsilon is either written to the register, or measured during conversions. The

value is represented in two's complement notation and in the range of -1.0 ≤ ε < 1.0, with the binary point to the

right of the MSB. Negative values have no significance.

6.2.8 Tamper Threshold (Tamperlevel) Register

Address: 18

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default = 828F5C = 2%

Tamper Threshold (Tamperlevel) sets the level at which the two active powers, PActive or P2Active, can differ be-

fore a tamper condition is detected. When this threshold is reached the CS5464 will use the higher of the two

power calculation in the pulse out accumulation registers. The value is represented in two's complement nota-

tion and in the range of -1.0 ≤ Tamperlevel < 1.0, with the binary point to the right of the MSB.

6.2.9 Cycle Count Register

Address: 19

MSB

LSB

223 222 221 220 219 218 217 216 .....

26

25

24

23

22

21

20

Default = 0x000FA0 = 4000

Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,

the computation cycle frequency is (MCLK/K)/(1024∗N). A one second computational cycle period occurs when

MCLK = 4.096 MHz, K = 1, and N = 4000. The Cycle Count register must be ≥ 2.

36

DS682PP1

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