CS5464-IS 查看數據表（PDF） - Cirrus Logic

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CS5464-IS

Three-channel, Single-phase Power/Energy IC

Cirrus Logic 

CS5464

6.2 Page 1 Registers

6.2.1 Current DC Offset (Idcoff, I2dcoff) and Voltage DC Offset (Vdcoff, V2dcoff) Registers

Address: 0 (Idcoff), 2 (Vdcoff), 7 (I2dcoff), 9 (V2dcoff)

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default = 0x000000

The DC Offset registers (Idcoff,Vdcoff, I2dcoff,V2dcoff) are initialized to 0.0 on reset. When DC Offset calibration is

performed, the register is updated with the DC offset measured over a computation cycle. DRDY will be set at

the end of the calibration. This register may be read and stored for future system offset compensation. The value

is represented in two's complement notation and in the range of -1.0 ≤ Idcoff, Vdcoff < 1.0

(-1.0 ≤ I2dcoff, V2dcoff < 1.0), with the binary point to the right of the MSB. See Section 7.1.2.1 DC Offset Calibra-

tion Sequence on page 39 for more information.

6.2.2 Current Gain (Ign, I2gn) and Voltage Gain (Vgn, V2gn) Registers

Address: 1 (Ign), 3 (Vgn), 8 (I2gn), 10 (V2gn)

MSB

LSB

21

20

2-1

2-2

2-3

2-4

2-5

2-6

..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22

Default = 0x400000 = 1.000

The gain registers (Ign,Vgn, I2gn,V2gn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is

performed, the register is updated with the gain measured over a computation cycle. DRDY will be set at the

end of the calibration. This register may be read and stored for future system gain compensation. The value is

in the range 0.0 ≤ Ign,Vgn < 3.9999 (0.0 ≤ I2gn,V2gn < 3.9999), with the binary point to the right of the second

MSB.

6.2.3 Power Offset (Poff, P2off) Registers

Address: 4 (Poff), 11 (P2off)

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default = 0x000000

Power Offset (Poff, P2off) is added to the instantaneous power being accumulated in the Pactive (P2active) regis-

ter, and can be used to offset contributions to the energy result that are caused by undesirable sources of energy

that are inherent in the system. The value is represented in two's complement notation and in the range of

-1.0 ≤ Poff < 1.0 (-1.0 ≤ P2off < 1.0), with the binary point to the right of the MSB.

6.2.4 Current AC Offset (Iacoff, I2acoff) and Voltage AC Offset (Vacoff, V2acoff) Registers

Address: 5 (Iacoff), 6 (Vacoff), 12 (I2acoff), 13 (V2acoff)

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default = 0x000000

The AC Offset Registers (Vacoff, Iacoff, V2acoff, I2acoff) are initialized to zero on reset, allowing for uncalibrated normal

operation. AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cy-

cles (where N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration.

34

DS682PP1

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