CS5346 查看數據表（PDF） - Cirrus Logic

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CS5346

103 dB, 192 kHz, Stereo Audio ADC with 6:1 Input Mux

Cirrus Logic 

7. REGISTER DESCRIPTION

CS5346

7.1 Chip ID - Register 01h

7

PART3

6

PART2

5

PART1

4

PART0

3

REV3

2

REV2

1

REV1

0

REV0

Function:

This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b, and the remaining bits

(3 through 0) indicate the device revision as shown in Table 4 below.

REV[3:0]

0000

Revision

A1

Table 4. Device Revision

7.2 Power Control - Address 02h

7

Freeze

6

Reserved

5

Reserved

4

Reserved

3

PDN_MIC

2

PDN_ADC

1

Reserved

0

PDN

7.2.1 Freeze (Bit 7)

Function:

This function allows modifications to be made to certain control port bits without the changes taking effect

until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the

Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed

in Table 5.

Name

Mute

Gain[5:0]

Gain[5:0]

Register

04h

07h

08h

Bit(s)

2

5:0

5:0

Table 5. Freeze-able Bits

7.2.2 Power-Down MIC (Bit 3)

Function:

The microphone preamplifier block will enter a low-power state whenever this bit is set.

7.2.3 Power-Down ADC (Bit 2)

Function:

The ADC pair will remain in a reset state whenever this bit is set.

7.2.4 Power-Down Device (Bit 0)

Function:

The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and

must be cleared before normal operation can occur. The contents of the control registers are retained

when the device is in power-down.

30

DS861PP1

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