CS5346 查看數據表（PDF） - Cirrus Logic

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CS5346

103 dB, 192 kHz, Stereo Audio ADC with 6:1 Input Mux

Cirrus Logic 

CS5346

7.3 ADC Control - Address 04h

7

FM1

6

5

4

FM0

Reserved

DIF

3

Reserved

2

1

0

Mute

HPFFreeze

M/S

7.3.1 Functional Mode (Bits 7:6)

Function:

Selects the required range of sample rates.

FM1

0

0

1

1

FM0

0

1

0

1

Mode

Single-Speed Mode: 8 to 50 kHz sample rates

Double-Speed Mode: 50 to 100 kHz sample rates

Quad-Speed Mode: 100 to 200 kHz sample rates

Reserved

Table 6. Functional Mode Selection

7.3.2 Digital Interface Format (Bit 4)

Function:

The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format

bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4.

DIF

0

1

7.3.3 Mute (Bit 2)

Description

Left-Justified (default)

I²S

Format

0

1

Table 7. Digital Interface Formats

Figure

3

4

Function:

When this bit is set, the serial audio output of the both channels is muted.

7.3.4 High-Pass Filter Freeze (Bit 1)

Function:

When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and

continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on

page 22.

7.3.5 Master / Slave Mode (Bit 0)

Function:

This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master

Mode, while clearing this bit selects Slave Mode.

DS861PP1

31

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