CS4525(2008) 查看數據表（PDF） - Cirrus Logic

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CS4525
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

CS4525

9.20.1 SRC Lock State Transition Interrupt (SRCLock)

Function:

This bit is read only. When set, indicates that the SRC has transitioned from an unlock to lock state or

from a lock state to an unlock state since the last read of this register. Conditions which cause the SRC

to transition states, such as loss of LRCK, SCLK, an LRCK ratio change, or the SRC achieving lock, will

cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read

of this register.

If this bit is set, indicating a SRC state change condition, and the SRCLockM bit is set, the INT pin will go

active. To determine the current lock state of the SRC, read the SRCLockSt bit in the interrupt status reg-

ister.

SRCLock Setting

SRC Lock State Change Status

0 .......................................... SRC lock state unchanged since last read of this register.

1 .......................................... SRC lock state changed since last read of this register.

9.20.2 ADC Overflow Interrupt (ADCOvfl)

Function:

This bit is read only. When set, indicates that an over-range condition occurred anywhere in the CS4525

ADC signal path and has been clipped to positive or negative full scale as appropriate since the last read

of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this

register.

If this bit is set, indicating an ADC over-range condition, and the ADCOvflM bit is set, the INT pin will go

active. To determine the current overflow state of the ADC, read the ADCOvflSt bit in the interrupt status

register.

ADCOvfl Setting

ADC Overflow Event Status

0 .......................................... ADC overflow condition has not occurred since last read of this register.

1 .......................................... ADC overflow condition has occurred since last read of this register.

9.20.3 Channel Overflow Interrupt (ChOvfl)

Function:

This bit is read only. When set, indicates that the magnitude of an output sample on channel 1, 2, or the

Sub channel has exceeded full scale and has been clipped to positive or negative full scale as appropriate

since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following

a read of this register.

If this bit is set, indicating a channel over-range condition, and the ChOvflM bit is set, the INT pin will go

active. To determine the current overflow state of each channel, read the ChXOvflSt and SubOvflSt bits

in the interrupt status register.

ChOvfl Setting

Channel Overflow Event Status

0 .......................................... A channel overflow condition has not occurred since last read of this register.

1 .......................................... A channel overflow condition has occurred since last read of this register.

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DS726PP3

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