CS4525(2008) 查看數據表（PDF） - Cirrus Logic

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CS4525
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

CS4525

9.20.4 Amplifier Error Interrupt Bit (AmpErr)

Function:

This bit is read only. When set, indicates that an error was detected in the power amplifier section since

the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a

read of this register. This bit is the logical OR of all the bits in the amplifier error status register. Read the

amplifier error status register to determine which condition occurred.

If this bit is set, indicating an amplifier stage error condition, and the AmpErrM bit is set to a ‘1’b, the INT

pin will go active. To determine the actual current state of the amplifier error condition, read the amplifier

error status register.

AmpErr Setting

Amplifier Error Event Status

0 ..........................................An amplifier error condition has not occurred since last read of this register.

1 ..........................................An amplifier error condition has occurred since last read of this register.

9.20.5 Mask for SRC State (SRCLockM)

Default = 0

Function:

This bit serves as a mask for the SRC status interrupt source. If this bit is set, the SRCLock interrupt is

unmasked, meaning that if the SRCLock bit is set, the INT pin will go active. If the SRCLockM bit is

cleared, the SRCLock condition is masked, meaning that its occurrence will not affect the INT pin. How-

ever, the SRCLock and SRCLockSt bits will continue to reflect the lock status of the SRC.

SRCLockM Setting

SRCLock INT Pin Mask State

0 ..........................................SRCLock condition masked.

1 ..........................................SRCLock condition un-masked.

9.20.6 Mask for ADC Overflow (ADCOvflM)

Default = 0

Function:

This bit serves as a mask for the ADC overflow interrupt source. If this bit is set, the ADCOvfl interrupt is

unmasked, meaning that if the ADCOvfl bit is set, the INT pin will go active. If the ADCOvflM bit is cleared,

the ADCOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the

ADCOvfl and ADCOvflSt bits will continue to reflect the overflow state of the ADC.

ADCOvflM Setting

ADCOvfl INT Pin Mask State

0 ..........................................ADCOvfl condition masked.

1 ..........................................ADCOvfl condition un-masked.

9.20.7 Mask for Channel X and Sub Overflow (ChOvflM)

Default = 0

Function:

This bit serves as a mask for the channel 1, 2, and Sub overflow interrupt source. If this bit is set, the ChO-

vfl interrupt is unmasked, meaning that if the ChOvfl bit is set, the INT pin will go active. If the ChOvflM bit

is cleared, the ChOvfl condition is masked, meaning that its occurrence will not affect the INT pin. How-

ever, the ChOvfl, ChXOvflSt, and SubOvflSt bits will continue to reflect the overflow state of the individual

channels.

ChOvflM Setting

ChOvfl INT Pin Mask State

0 ..........................................ChOvfl condition masked.

1 ..........................................ChOvfl condition un-masked.

DS726PP3

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