CS4525(2008) 查看數據表（PDF） - Cirrus Logic

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CS4525
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

CS4525

9.19.5 Power Down PWM Power Output X (PDnOutX)

Default = 1

Function:

When set, the specific PWM power output will enter a power-down state. Only the output power stage is

powered down. The PWM modulator is not affected, nor is the setup or delay register values. When set

to normal operation, the specific output will power up according to the state of the RmpSpd[1:0] bits and

the channel output configuration selected. When transitioning from normal operation to power down, the

specific output will power down according to the state of the RmpSpd[1:0] bits and the channel output con-

figuration selected.

PDnChX Setting

Power Output X Power-Down State

0 ..........................................Normal power output X operation.

1 ..........................................Power output X power-down enabled.

The entire divide will enter a low-power state when this function is enabled:

9.19.6 Power Down (PDnAll)

Default = 1

Function:

The CS4525 will enter a power-down state when this function is enabled:

1. The power PWM outputs will be held in a high-impedance state.

2. The logic-level PWM outputs will continuously drive a logic ‘0’ if the HiZPSig bit is set and will be held

in a high-impedance state if the HiZPSig bit is clear.

3. AUX_SDOUT, the auxiliary serial data output, will be driven to a digital-low. AUX_LRCK and

AUX_SCLK, the auxiliary serial output’s clocks, will continue to operate if the EnAuxPort bit is set,

ADC/SP is cleared, and the serial audio input receives a valid SCLK and LRCK; otherwise they will

also be driven to a digital-low voltage.

4. DLY_SDOUT, the delay serial data output, will output the unprocessed audio data from SDATA if

EnAuxPort is set, DlyPortCfg[1:0] is configured for serial output delay interface, ADC/SP is cleared,

and the serial audio input port receives a valid SCLK, LRCK, and SDATA. Otherwise, it will drive a

low voltage.

The contents of the control registers are retained in this state. Once the PDnAll bit is disabled, the pow-

ered and logic-level PWM outputs will first perform a click-free start-up function and then resume normal

operation.

The PDnAll bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur.

PDnAll Setting

Device Power-Down State

0 ..........................................Normal device operation.

1 ..........................................Device power-down enabled.

9.20 Interrupt (Address 60h)

7

SRCLock

6

ADCOvfl

5

ChOvfl

4

AmpErr

3

2

1

SRCStateM ADCOvflM ChOvflM

0

AmpErrM

Bits [7:4] in this register are read only. A ‘1’b in these bit positions indicates that the associated condition has oc-

curred at least once since the register was last read. A ‘0’b indicates that the associated condition has not occurred

since the last reading of the register. Reading the register resets bits to [7:4] ‘0’b. These bits are considered “edge-

triggered” events. The operation of these 4 bits is not affected by the interrupt mask bits and the condition of each

bit can be polled instead of generating an interrupt as required.

DS726PP3

89

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